The use of metals such as copper and cobalt as a conductive interconnect material is favored in semiconductor devices because of the high electrical conductivities and circuit speeds these metals enable. On the other hand, such metals are difficult to pattern. As such, copper interconnect leads have predominantly heretofore been formed using damascene and dual damascene processing technology whereby openings are formed in a dielectric layer on a substrate such as a semiconductor substrate used to form semiconductor devices. Copper is deposited over the dielectric layer and within the openings. Polishing/planarization removes copper from over the dielectric leaving the copper inlaid within the openings. In this way, the burden on photolithography is shifted from copper to the more manageable dielectric layer. The inlaid copper includes an upper surface that is essentially co-planar with the top surface of the patterned dielectric layer in which the copper is formed.
Subtractive metal etching is an alternative to a damascene process flow. A contiguous layer of metal is deposited and then patterned to form horizontal electrical interconnections. One process employed to perform subtractive metal etching uses a plasma. The plasma selectively removes the metal, however it may redeposit metal-containing residues on the substrate as well as within the processing chamber. Such residues can be difficult to remove and may have deleterious effects on the semiconductor device as well as the chamber.